1. Field of the Invention
The present invention relates generally to digital logic receivers and transmitters.
2. Description of the Related Art
Transmitters and receivers (or transceivers when paired) for generating and receiving digital logic signals which are transmitted over transmission lines, are well known and in widespread use. Common circuit configurations for these devices include Low Voltage Differential Signaling (LVDS), Emitter Coupled Logic (ECL) and Pseudo Emitter Coupled Logic (PECL), Current Mode Logic (CML), Gunning Transceiver Logic (GTL) and Full Swing CMOS. A number of different transmitter, receiver and related circuits are disclosed, for example, in the following U.S. Patents:
Current mode logic transceivers, those in which the digital logic states are represented by current signals having two or more different predetermined levels or magnitudes, are disclosed, for example, in the Leung U.S. Pat. No. 5,030,855 and the Beers et al. U.S. Pat. No. 5,578,939. The Leung patent is directed to a transceiver for communication across a capacitively loaded line, and includes a receiver having a current mirror. The current mirror includes a pair of similar transistors, one of which is in a configuration known as a xe2x80x9cdiode-connectxe2x80x9d circuit. The diode connect configuration is said to minimize the voltage swing developed on the capacitive line to enable high speed communication.
The Beers et al. U.S. Pat. No. 5,578,939 is directed to a bi-directional transmission line driver/receiver. The receiver has an active terminator which includes a terminating FET for sinking the current sourced by the driver. The impedance of the terminating FET is said to be controlled by another FET in response to a bias voltage signal to adjust the impedance of the terminating FET to match the impedance of the transmission line. The bias voltage signal is provided by a reference generator to set the impedance family and current magnitude interactively and continuously using a separate reference line as a feedback path.
There remains, however, a continuing need for improved current mode logic transceivers and associated components. A transceiver capable of reliable and high-quality data communications at data transfer rates approaching and exceeding those in the range of a gigabit per second over relatively low impedance (e.g., 30-50 ohms) transmission lines would be desirable. A transceiver of this type which can operate at relatively low current levels (e.g., less than about 5 mA) would be especially desirable. Such a transceiver which can be relatively efficiently implemented (e.g., CMOS with few transistors) while at the same time offering robust manufacturing characteristics is preferred. Still further advantages would be provided if the transceiver was self-terminating so that metal interconnects in the packages in which they are enclosed do not behave as electrical stubs.
The present invention is an improved logic receiver for interconnection to a transmission line having a uniform characteristic impedance. The receiver can be efficiently implemented using conventional CMOS and other transistor technologies and is robust to manufacturing variations. Simulations have demonstrated the receiver""s capability of reliably achieving data transfer rates exceeding 2.5 gigabits per second over a 30 ohm transmission line at current levels between 1 and 3 mA.
One embodiment of the receiver includes a transmission line input terminal for receiving first and second non-zero current level digital logic signals (i.e., predefined logic level currents), a current mirror and a load. The current mirror includes first and second FETs. The first FET is connected to the transmission line input terminal and configured to provide nonlinear current/voltage characteristics between the first and second current levels which approximate the characteristic impedance of the transmission line so the first FET absorbs the current of the digital logic signals. The second FET is connected to the first FET and provides a mirror current having current levels proportional to the current levels of the digital logic signals. The load, which is connected to the second FET of the current mirror, receives the mirror current and produces voltage level signals representative of the digital logic signals. In a preferred embodiment, the first FET has a gate which is connected to the drain, and the channel is sized so the FET approximates the characteristic impedance of the transmission line over the predefined logic level currents.